ASSETCASTING

Semiconductor fabrication

Explore industry roles in designing chips, depositing and removing materials to form circuits, and connecting and verifying them.

Select equipment to explore the process and related companies.

How to read this map

Select equipment to explore processes and companies.

Design & applicationsWaferDepositionLithographyCleaningEtchingMetrology & testingPackaging
All processes
Map limitations

This is an abbreviated educational map, not a single standard path for actual fabrication. Sequences, repetitions, and materials differ between memory and logic, products, and process generations. Oxidation, ion implantation, heat treatment, planarization, interconnect formation, and other operations are not all shown as separate nodes. Companies illustrate roles based on public products and technologies; they are not lists of exclusive suppliers or verified counterparties. Economic significance and watch points are principle-based educational interpretations, not forecasts of earnings or share prices or investment recommendations.

Educational diagram. Actual factory layouts and equipment proportions differ, and many processes repeat.

Back-end assembly

Packaging and connections

Protect chips and electrically connect them to external components or other chips.

Concept diagram · not to scale

Related companies

Samsung Electronics

An example here of foundry manufacturing, design support, and packaging roles

Amkor Technology

Semiconductor packaging and wafer/package testing services

ASE

SiP and packaging technologies integrating multiple chips

SK hynix

DRAM memory, including HBM, and stacking technology

Process explanation

Packaging connects and protects dies so they can be used in systems. Approaches include SiP integrating multiple chips in a package, and 2.5D and 3D. Connections and thermal management both matter; not all packages have the same structure.

Industry perspective

Why it matters

Examining inter-chip connections and assembly conditions, not only individual-chip performance, helps explain the relationship between system performance and cost.

Indicators to watch

  • How do connections and thermal management change when multiple chips are combined?
  • Were assembly difficulty and the test plan considered together?
Sources